The power consumed by integrated circuits can be a critical factor in their performance in certain applications. For example, the power consumed by memory devices used in portable personal computers greatly affects the length of time they can be used without the need to recharge batteries powering such computers. Power consumption can also be important where memory devices are not powered by batteries because it may be necessary to limit the heat generated by the memory devices.
In general, the power consumption of memory devices increases with both the capacity and the operating speed of memory devices. The power consumed by memory devices is also affected by their operating mode. A dynamic random access memory (“DRAM”), for example, will generally consume a relatively large amount of power when the memory cells of the DRAM are being refreshed. During a refresh of a DRAM, rows of memory cells in a memory cell array are being actuated in rapid sequence. Each time a row of memory cells is actuated, a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated, thereby consuming a significant amount power. As the number of columns in the memory cell array increases with increasing memory capacity, the power consumed in actuating each row increases accordingly. Power consumption also increases with increases in the rate at which the rows of memory cells are actuated. Thus, as the operating speed and capacity of DRAMs continues to increase, so also does the power consumed by DRAMs continue to increase during refresh.
The refresh power consumption of a DRAM is directly proportional to the refresh rate required to maintain voltages stored in memory cell capacitors within a range in which the voltages can be accurately determined by sense amplifiers. Therefore, if the required refresh rate for a DRAM could be reduced, so also could the refresh power consumption.
With reference to FIG. 1, a portion of a typical DRAM array 100 includes a plurality of memory cells 110, each of which is coupled to a word line WL and a digit line DL. The memory cells 110 in the array 100 are arranged in rows and columns, with a word line being provided for each row of memory cells 100. The word lines WL are coupled to and actuated by a row decoder 112 responsive to a row address A0-AX. As shown in FIG. 1, the DRAM array 100 has a folded digit line architecture so that complimentary digit lines DL and DL* are provided for each column of memory cells 110. In a memory array having an open digit line architecture (not shown), a single digit line DL is included in the array for each column of memory cells 110. The other digit line is provided by an adjacent array. However, the following discussion of the problems with DRAM arrays and prior attempts to solve such problems is applicable to arrays having an open digit line architecture as well as arrays having a folded digit line architecture.
Regardless of whether the array has a folded digit line architecture or an open digit line architecture, each memory cell 110 includes a memory cell capacitor 114 coupled between a cell plate 116 and a storage node 118. An access transistor 120 is coupled between the storage node 118 and a digit line DL for the column containing the memory cell 110. The gate of the access transistor 120 is coupled to a word line WL for the row containing the memory cell 110. When a data bit is to be written to the memory cell 110, a voltage corresponding to the data bit, generally either VCC or zero volts, is applied to the digit line DL to which the memory cell 110 is coupled, and the voltage applied to the word line WL is driven high to turn ON the access transistor 120. The access transistor then couples the digit line DL to the capacitor 114 to store the voltage of the digit line DL in the capacitor 114. For a read operation, the digit line DL is first equilibrated to an equilibration voltage, generally to VCC/2, and the word line WL is then driven high to turn ON the access transistor 120. The access transistor 120 then couples the capacitor 114 to the digit line DL to slightly alter the voltage on the digit line DL above or below the equilibration voltage depending upon the voltage stored in the capacitor 114. An n-sense amplifier 130 and a p-sense amplifier 132 sense whether the voltage has increased or decreased responsive to applying an active low NSENSE* signal of normally zero volts to the n-sense amplifier 130 and applying an active high PSENSE signal of normally VCC to the p-sense amplifier 132. The NSENSE* signal and the PSENSE signal are supplied by control circuitry (not shown) in a DRAM. If a voltage increase was sensed, the p-sense amplifier 132 drives the digit line DL to VCC, and, if a voltage decrease was sensed, the n-sense amplifier 130 drives the digit line DL to zero volts. The voltage applied to the digit line DL by the sense amplifiers 130, 132 then recharges the capacitor 114 to the voltage to which it was originally charged. A column decoder 136 couples one of the pairs of complimentary digit lines DL, DL* to complimentary input/output lines “IO, IO* responsive to a column address A0-AY.
The above-described memory read process of activating a word line WL and then sensing the digit line voltage of all memory cells 100 in the row for the active word line WL is what is done to refresh the memory cells 100. If the voltage on the capacitor 114 has been excessively discharged from VCC or excessively charged from zero volts between refreshes, it can be impossible for the sense amplifiers 130, 132 to accurately read the voltage to which the memory cell capacitor 114 was charged. The result is an erroneous reading of the memory cell 100 known as a data retention error.
As is well known in the art, the charge placed on a memory cell capacitor 114 dissipates through a variety of paths. One discharge path is through the dielectric of the capacitor 114 itself. Another significant discharge path is through the access transistors 120 coupling the capacitors 114 to the digit lines DL when the transistors 120 are turned OFF. This leakage current is known as the “sub-threshold” leakage current of the transistors 120. Reducing the sub-threshold leakage current of the access transistors 120 allows the capacitor 114s to retain a voltage that is close enough to the voltage initially placed on the capacitors 114 for a data retention error to be avoided.
Various approaches have been used to reduce the sub-threshold leakage of the access transistors 120 to allow memory cell capacitors 114 to retain charge for a longer period between refreshes. Some of these approaches rely on increasing the threshold voltage VT of the access transistor 120. As is well known in the art, the threshold voltage VT is the gate-to-source voltage at which the transistor 120 begins to turn ON so that it can readily conduct current. However, the value of the gate-to-source voltage in relation to the threshold voltage VT also determines the amount of sub threshold leakage through the access transistor 120 when the transistor 120 is OFF. For example, for a given gate-to-source voltage, an access transistor 120 having a threshold voltage VT of 0.8 volts will conduct less current than an access transistor 120 having a threshold voltage VT of 0.6 volts. Also, for a given threshold voltage VT, an access transistor 120 having a gate-to-source voltage of −0.5 volts will conduct less current than an access transistor 120 having a gate-to-source voltage of 0 volts.
An important parameter affecting the threshold voltage VT an access transistor 120 is the voltage of the substrate in which the transistor 120 is fabricated. Making the substrate more negative increases the threshold voltage VT for a given gate-to-source voltage. In the past, the substrate in which DRAMs are fabricated has been biased to a negative voltage, generally by using a negative voltage charge pump (not shown). While this approach successfully reduces the sub-threshold leakage current of the access transistors 120 and consequently reduces the required refresh rate, it creates other problems for the DRAMs. For example, since charge pumps are inherently very inefficient in converting one voltage to another, the need for a charge pump can unduly increase the power consumption of a DRAM. Also, negatively biasing the entire substrate in which the DRAM is fabricated can cause other circuitry, such as output buffers for the DRAM, to “lock up” and pull the voltage of the substrate to a positive voltage, such as VCC. When this happens, the DRAM becomes inoperative.
The disadvantages of negatively biasing the entire substrate for the DRAM have been addressed by electrically isolating the substrate for the memory array from the substrate for the remaining circuitry in the DRAM, and then negatively biasing only the substrate for the memory array. Although this approach does reduce the power consumed by a negative voltage charge pump and does prevent other circuitry from being affected by the negative substrate voltage, it creates other problems. With reference to FIG. 2, a “triple well” 140 is normally used to isolate the memory array from the remaining circuitry in the DRAM. When formed in a p-type substrate 144, for example, the triple well 140 is formed by a buried n-type layer 146 normally formed by ion implantation, and two relatively deep and narrow n-wells 148, 150 extending from the surface of the substrate 144 to the layer 146. A p-well 154 is thereby formed in the triple well 140, and an array 156 of memory cells are fabricated in the p-well 154. Other circuitry 158 in the DRAM is fabricated in the substrate 144 outside of the p-well 154 so that the circuitry is electrically isolated from the p-well 154 by the triple well 140. The p-well 154 is biased to a negative voltage by suitable means, such as a charge pump (not shown), to reduce the sub-threshold leakage current of the access transistors 120, and the substrate 144 is biased to zero volts simply by coupling the substrate to a ground terminal.
Although the triple well 140 shown in FIG. 2 does provide the advantages of a low sub-threshold leakage current while avoiding the above-described disadvantages of a negative biasing the entire substrate 144, it has the significant disadvantage of consuming a relatively large area of the substrate 144. More specifically, it is difficult to fabricate the n-wells 148, 150 deeply without the n-wells also spreading out to occupy an undesirably large area of the substrate 144. As a result, DRAMs using this approach must be relatively large, which adversely affects the cost and operating speed of such DRAMs.
As previously explained, the sub-threshold leakage current of the access transistor 120 is determined by the gate-to-source voltage in relation to the threshold voltage VT. Rather than attempting to increase the threshold voltage VT, another approach that has been used is to decrease the gate-to-source voltage when the transistors 120 are OFF. With reference to FIG. 1, the gate-to-source voltage can be decreased by biasing the digit lines DL more positively when the access transistors 120 in one row are turned ON and the access transistors 120 in the remaining rows are turned OFF. As explained above, when a row of memory cells 100 are being read, one of the word lines WL is activated to couple the memory cell capacitors 114 in that row to respective digit lines DL. After the sense amplifiers 130, 132 have sensed the voltage of the capacitors 114, the digit lines DL are held at the sensed voltage for as long as the word line WL is active. This can be a considerable period, e.g., up to 120 MS., because data may be read sequentially from each column of an active row, which can require considerable time. During the time that a digit line DL is held at zero volts by the n-sense amplifier 130, the gate-to-source voltage of the access transistors 120 in all of the other rows is relatively low, since the voltage of the other word lines WL may also be at zero volts. As a result, the sub threshold leakage current from the memory cell capacitors 114 in the inactive rows can be considerable, thereby decreasing the time between refreshes of the memory cells.
One approach to reducing the sub threshold current leakage of the access transistors 120 is to power the n-sense amplifiers 130 with a positive voltage, such as 0.3 volts, instead of zero volts. The n-sense amplifiers 130 then drive the digit lines DL to the positive voltage so that the digit lines DL are never held at zero volts. Prior art techniques using this approach are described in U.S. Pat. No. 4,679,172 to Kirsch et al. and an article by Asakura et al. entitled “A 34 ns 256 Mb DRAM with Boosted Sense-Ground Scheme,” 1994 IEEE International Solid State Circuits Conference, pp. 140-41.
Another similar approach makes the gate-to-source voltage of more negative by adjusting the voltage of the word lines WL. The word lines WL are normally driven to a pumped voltage in excess of VCC to turn ON the access transistors 120 and allow them to coupled VCC from the digit lines DL to the memory cell capacitors 114. The word lines WL are normally driven to zero volts to turn OFF the access transistors 120 to isolate the memory cell capacitors 114 from the digit lines DL. Rather than driving the word lines to zero volts to turn OFF the access transistors 120, the word lines can instead be coupled to a negative voltage to turn OFF the access transistors 120. Making the OFF voltage of the word lines WL negative reduces the sub-threshold leakage current of the access transistors, as previously explained, thereby reducing the required refresh rate.
These techniques for reducing the sub-threshold leakage of the transistors 120 by reducing the gate-to-source voltage of the transistors 120 avoid the problems described above encountered by negatively biasing all or a portion of the substrate. However, these techniques create other problems that can impair the performance and/or expense of DRAMs. For example, the technique of biasing the word lines WL to a negative voltage still generally requires the use of a negative charge pump. For the technique of biasing the digit lines to a positive voltage to work well, the bias voltage must be precisely controlled. Unfortunately, it is difficult to achieve precise control of voltages with MOSFET transistors typically used in DRAMs. As a result, this approach to has not met with much practical success.
There is therefore the need for a circuit and method for providing a precisely controlled bias voltage to the digit lines DL of DRAMs to reducing the sub threshold leakage current of access transistors used in the DRAMs. As previously described, reducing the sub threshold leakage current would allow DRAMs to be refreshed at a slower rate, thereby reducing power consumption.